基于TI公司的AM437x双照相机参考设计

TI公司的高性能处理器AM437x系列MCU是基于ARM Cortex-A9核,具有增强的3D图像加速子系统POWERVR SGX以及用于包括工业通信协议如EtherCAT, PROFIBUS®, EnDat和其它协议的实时处理的协处理器,器件支持高级操作系统(HLOS),主要用在工业自动化,POS,手持无线电,测试测量,病人监护,手持数据终端,导航设备和条码扫描仪.本文介绍了AM437x 系列主要特性和框图, 双照相机参考设计和AM437x GP EVM评估模块主要特性,系统框图,电路图,材料清单和PCB设计文件.

　　The TI AM437x high-performance processors are based on the ARM Cortex-A9 core. The processors are enhanced with 3D graphics acceleration for rich graphical user interfaces, as well as a co-processor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS®, EnDat and others. The devices support high-level operating systems (HLOS). Linux® is available free of charge from TI. Other HLOSs are available from TI’s Design Network and ecosystem partners.

　　These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2.

　　The processors contain the subsystems shown in and a brief description of each follows.

　　The processor subsystem is based on the ARM Cortex-A9 core, and the POWERVR SGX graphics accelerator subsystem provides 3D graphics acceleration to support display and advanced user interfaces.

　　The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the system-on-chip (SoC).

　　High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.

　　One on-chip analog to digital converter (ADC0) can couple with the display subsystem to provide an integrated touch-screen solution. The other ADC (ADC1) can combine with the pulse width module to create a closed-loop motor control solution.

　　The real-time clock (RTC) provides a clock reference on a separate power domain. The clock reference enables battery backed clock reference.

　　The camera interface offers configuration for a single or dual camera parallel port.

　　Cryptographic acceleration is available in every AM437x device. Secure boot can also be made available for anti-cloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.

　　AM437x 系列主要特性:

　　Highlights

　　Up to 1000-MHz Sitara ARM Cortex-A9 32-Bit RISC processor

　　NEON SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor

　　32KB of Both L1 Instruction and Data Cache

　　256KB of L2 Cache or L3 RAM

　　32-Bit LPDDR2, DDR3, and DDR3L Support

　　General-Purpose Memory Support (NAND, NOR, SRAM) Supporting Up to 16-bit ECC

　　SGX530 Graphics Engine

　　Display Subsystem

　　Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)

　　Real-Time Clock (RTC)

　　Up to Two USB 2.0 High-Speed OTG Ports with Integrated PHY

　　10, 100, and 1000 Ethernet Switch Supporting Up to Two Ports

　　Serial Interfaces:

　　Two Controller Area Network (CAN) Ports

　　Six UARTs, Two McASPs, Five McSPI, Three I2C Ports, One QSPI and One HDQ or 1-Wire

　　Security

　　Crypto Hardware Accelerators (AES, SHA, RNG, DES and 3DES)

　　Secure Boot

　　Two 12-Bit Successive Approximation Register (SAR) ADCs

　　Up to Three 32-Bit Enhanced Capture Modules (eCAP)

　　Up to Three Enhanced Quadrature Encoder Pulse Modules (eQEP)

　　Up to Six Enhanced High-Resolution PWM Modules (eHRPWM)

　　MPU Subsystem

　　Up to 1000-MHz ARM Cortex-A9 32-Bit RISC Microprocessor

　　32KB of Both L1 Instruction and Data Cache

　　256KB of L2 Cache (Option to Configure as L3 RAM)

　　256KB of On-Chip Boot ROM

　　64KB On-Chip RAM

　　Secure Control Module (SCM)

　　Emulation and Debug

　　JTAG

　　Embedded Trace Buffer

　　Interrupt Controller

　　On-Chip Memory (Shared L3 RAM)

　　256KB of General Purpose On-Chip Memory Controller (OCMC) RAM

　　Accessible to All Masters

　　Supports Retention for Fast Wakeup

　　Up to 512KB of Total Internal RAM

　　(256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)

　　External Memory Interfaces (EMIF)

　　DDR Controllers:

　　LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)

　　DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)

　　32-Bit Data Bus

　　2GB of Total Addressable Space

　　Supports One x32, Two x16, or Four x8 Memory Device Configurations

　　General-Purpose Memory Controller (GPMC)

　　Flexible 8- and 16-Bit Asynchronous Memory Interface with Up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)

　　Uses BCH Code to Support 4-, 8-, or 16-Bit ECC

　　Uses Hamming Code to Support 1-Bit ECC

　　Error Locator Module (ELM)

　　Used with the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm

　　Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms

　　Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)

　　Supports Protocols such as EtherCAT, PROFIBUS, PROFINET, and EtherNet/IP™, EnDat 2.2, and More

　　Two Programmable Real-Time Units (PRUs) Subsystems

　　32-Bit Load and Store RISC Processor Capable of Running at 200 MHz

　　12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM with Single-Error Detection (Parity)

　　8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM with Single-Error Detection (Parity)

　　Single-Cycle 32-Bit Multiplier with 64-Bit Accumulator

　　Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal

　　12KB (PRU-ICSS1 only) of Shared RAM with Single-Error Detection (Parity)

　　Three 120-Byte Register Banks Accessible by Each PRU

　　Interrupt Controller Module (INTC) for Handling System Input Events

　　Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS

　　Peripherals Inside the PRU-ICSS

　　One UART Port with Flow Control Pins, Supports Up to 12 Mbps

　　One Enhanced Capture (eCAP) Module

　　Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT

　　One MDIO Port

　　Industrial Communication is Supported by Two PRU-ICSS Subsystems

　　Power Reset and Clock Management (PRCM) Module

　　Controls the Entry and Exit of Deep-Sleep Modes

　　Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing

　　Clocks

　　Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks

　　Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption

　　Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals (MMC and SD, UART, SPI, I2C), L3, L4, Ethernet, GFX (SGX530), and LCD Pixel Clock)

　　Power

　　Two Non-Switchable Power Domains (RTC and Wake-Up Logic (WAKE-UP))

　　Three Switchable Power Domains (MPU Subsystem, SGX530 (GFX), Peripherals and Infrastructure (PER))

　　Implements SmartReflex Class 2B for Core Voltage scaling Based On Die Temperature, Process Variation and Performance (Adaptive Voltage Scaling (AVS))

　　Dynamic Voltage Frequency Scaling (DVFS)

　　Real-Time Clock (RTC)

　　Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information

　　Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO

　　Independent Power-On-Reset (RTC_PWRONRSTn) Input

　　Dedicated Input Pin (RTC_WAKEUP) for External Wake Events

　　Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wake Up or Cortex-A9 for Event Notification

　　Programmable Alarm Can Be Used with External Output (RTC_PMIC_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains

　　Peripherals

　　Up to Two USB 2.0 High-Speed OTG Ports with Integrated PHY

　　Up to Two Industrial Gigabit Ethernet MACs (10, 100, and 1000 Mbps)

　　Integrated Switch

　　Each MAC Supports MII, RMII, and RGMII and MDIO Interfaces

　　Ethernet MACs and Switch Can Operate Independent of Other Functions

　　IEEE 1588v2 Precision Time Protocol (PTP)

　　Up to Two Controller-Area Network (CAN) Ports

　　Supports CAN Version 2 Parts A and B

　　Up to Two Multichannel Audio Serial Ports (McASP)

　　Transmit and Receive Clocks Up to 50 MHz

　　Up to Four Serial Data Pins Per McASP Port with Independent TX and RX Clocks

　　Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats

　　Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)

　　FIFO Buffers for Transmit and Receive (256 Bytes)

　　Up to Six UARTs

　　All UARTs Support IrDA and CIR Modes

　　All UARTs Support RTS and CTS Flow Control

　　UART1 Supports Full Modem Control

　　Up to Five Master and Slave McSPI Serial Interfaces

　　McSPI0-McSPI2 Supports Up to Four Chip Selects

　　McSPI3-McSPI4 Supports Up to Two Chip Selects

　　Up to 48 MHz

　　One Quad-SPI

　　Supports eXecute In Place (XIP) from Serial NOR FLASH

　　One Dallas 1-Wire® and HDQ Serial Interface

　　Up to Three MMC, SD, and SDIO Ports

　　1-, 4-, and 8-Bit MMC, SD, and SDIO Modes

　　1.8- or 3.3-V Operation on All Ports

　　Up to 48-MHz Clock

　　Supports Card Detect and Write Protect

　　Complies with MMC4.3 and SD and SDIO 2.0 Specifications

　　Up to Three I2C Master and Slave Interfaces

　　Standard Mode (Up to 100 kHz)

　　Fast Mode (Up to 400 kHz)

　　Up to Six Banks of General-Purpose I/O (GPIO)

　　32 GPIOs per Bank (Multiplexed with Other Functional Pins)

　　GPIOs Can be Used as Interrupt Inputs (Up to Two Interrupt Inputs per Bank)

　　Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs

　　Twelve 32-Bit General-Purpose Timers

　　DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks

　　DMTIMER4–DMTIMER7 are Pinned Out

　　One Public Watchdog Timer

　　One Free Running High Resolution 32-kHz Counter (synctimer32K)

　　SGX530 3D Graphics Engine

　　Tile-Based Architecture Delivering Up to 20M Poly/sec

　　Universal Scalable Shader Engine is a Multi-Threaded Engine Incorporating Pixel and Vertex Shader Functionality

　　Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0

　　Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenVG 1.0

　　Fine-Grained Task Switching, Load Balancing, and Power Management

　　Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction

　　Programmable High-Quality Image Anti-Aliasing

　　Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture

　　Display Subsystem

　　Display Modes

　　Programmable Pixel Memory Formats (Palletized: 1-, 2-, 4-, and 8-Bit Per Pixel; RGB 16- and 24-Bit Per Pixel; and YUV 4:2:2)

　　256 x 24-Bit Entries Palette in RGB

　　Up to 2048 x 2048 Resolution

　　Display Support

　　Four Types of Displays Are Supported: Passive and Active Colors; Passive and Active Monochromes

　　4- and 8-Bit Monochrome Passive Panel Interface Support (15 Grayscale Levels Supported Using Dithering Block)

　　RGB 8-Bit Color Passive Panel Interface Support (3,375 Colors Supported for Color Panel Using Dithering Block)

　　RGB 12-, 16-, 18-, and 24-Bit Active Panel Interface Support (Replicated or Dithered Encoded Pixel Values)

　　Remote Frame Buffer (Embedded in the LCD Panel) Support through the RFBI Module

　　Partial Refresh of the Remote Frame Buffer through the RFBI Module

　　Partial Display

　　Multiple Cycles Output Format on 8-, 9-, 12-, and 16-Bit Interface (TDM)

　　Signal Processing

　　Overlay and Windowing Support for One Graphics Layer (RGB or CLUT) and Two Video Layers (YUV 4:2:2, RGB16, and RGB24)

　　RGB 24-bit Support on the Display Interface, Optionally Dithered to RGB 18-Bit Pixel Output Plus 6-Bit Frame Rate Control (Spatial and Temporal)

　　Transparency Color Key (Source and Destination)

　　Synchronized Buffer Update

　　Gamma Curve Support

　　Multiple-Buffer Support

　　Cropping Support

　　Color Phase Rotation

　　Two 12-Bit Successive Approximation Register (SAR) ADCs (ADC0, ADC1)

　　867K Samples Per Second

　　Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch

　　ADC0 Can Be Configured to Operate as a 4-, 5-, or 8-Wire Resistive Touch Screen Controller (TSC)

　　Up to Three 32-Bit Enhanced Capture Modules (eCAP)

　　Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs

　　Up to Six Enhanced High-Resolution PWM Modules (eHRPWM)

　　Dedicated 16-Bit Time-Base Counter with Time and Frequency Controls

　　Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs

　　Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules

　　Device Identification

　　Factory Programmable Electrical Fuse Farm (FuseFarm)

　　Production ID

　　Device Part Number (Unique JTAG ID)

　　Device Revision (Readable by Host ARM)

　　Feature Identification

　　Debug Interface Support

　　JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug

　　Supports Real-Time Trace Pins (for Cortex-A9)

　　64KB Embedded Trace Buffer (ETB)

　　Supports Device Boundary Scan

　　Supports IEEE 1500

　　DMA

　　On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTC) and One Third-Party Channel Controller (TPCC), Which Supports Up to 64 Programmable Logical Channels and Eight QDMA Channels

　　EDMA is Used for:

　　Transfers to and from On-Chip Memories

　　Transfers to and from External Storage (EMIF, General-Purpose Memory Controller, and Slave Peripherals)

　　Inter-Processor Communication (IPC)

　　Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS

　　Boot Modes

　　Boot Mode is Selected via Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin

　　Camera

　　Dual Port 8- and 10-Bit BT656 Interface

　　Dual Port 8- and 10-Bit Including External Syncs

　　Single Port 12-Bit

　　YUV422/RGB422 and BT656 Input Format

　　RAW Format

　　Pixel Clock Rate Up to 75 MHz

　　Package

　　491-pin BGA Package (17x17 mm) (ZDN Suffix), 0.65-mm Ball Pitch with Via Channel Array Technology to Enable Low-Cost Routing

　　AM437x系列主要应用:

　　Patient Monitoring

　　Navigation Equipment

　　Industrial Automation

　　Portable Data Terminals

　　Bar Code Scanners

　　Point of Service

　　Portable Mobile Radio

　　Test and Measurement

　　图1. AM437x功能框图

　　AM437x双照相机参考设计

　　Developers looking for camera support on the Sitara AM437x processors can use this reference design to jump start their development. The AM437x camera interface is a parallel port that can be configured as a single or dual camera interface. The dual camera configuration enables the use of two simultaneous camera inputs.

　　The AM437x GP EVM is a standalone test, development, and evaluation module system that enables developers to write software and develop hardware around an AM437x processor subsystem. The main elements of the AM437x subsystem are already available on the base board of the EVM, which gives developers the basic resources needed for most general purpose type projects that encompass the AM437x as the main processor. Furthermore, additional, "typical-type" peripherals are built into the EVM, such as memory, sensors, LCD, Ethernet physical layer (PHY), and so on, so that prospective systems can be modeled quickly without significant additional hardware resources.

　　AM437x GP EVM评估模块主要特性:

　　Two simultaneous 2-Megapixel SOC Cameras

　　Cameras connected to the integrated Camera Interface (VPFE) of the Sitara AM437x processor

　　Dual Port 8-bit interface with BT656 or external synch signals

　　YUV422/RGB422, BT656, and RAW interface formats

　　Complete sub-system reference with schematics, BOM, design files, and HW User’s Guide implemented on a fully assembled board developed for testing and validation.

　　图2. AM437x GP EVM评估模块外形图