RISC-V如何解决硬件碎片化的问题？

1导言

最近几年RISC-V的大火，让IC行业开始关注RISC-V这个迅猛发展的架构，但提到这个年轻的架构，大家最先想到的是，薄弱的生态，硬件的碎片化。RISC-V从发展之初就旨在提供高度模块化和可拓展的指令集，用户甚至可以自己拓展指令集，这种灵活性有利于特定方向的芯片优化。但随之而来的问题就是各个厂商对于拓展的支持各不相同，甚至有不少自己定义的指令集，让原本就生态脆弱的RISC-V竞争力更低，尤其是在软件生态依赖很强的高端应用场景。

2介绍

目前国际比较领先的RISC-V厂商，sifive，推出的几款RISC-V的IP，例如P670，>12 SpecINT2k6/GHz，性能大致在A78水平。而P870，>18 SpecINT2k6/GHz，性能则更进一步，靠近ARM的先进Core水准。不知道大家有没有关注到P670官网描述P670支持RVA22 profile specification，而P870支持的是RV23A profile specification。这里的RVA是什么？实际RVA本身的提出就是为了解决硬件厂商对芯片实现“脆片化”的问题。这个标准目前有三个，RVA，RVB，RVM，本文仅介绍RVA。

本质上RVA是对拓展实现种类和数量的要求，简单说就是如果宣称符合RVA规范，那么有些Spec里面的可选拓展将不再是“可选的”而是“强制”需要实现的。例如对压缩指令C拓展不是标准必须要实现的，但在RVA里则是强制需要实现的，否则就不是RVA标准。RVA同样分版本，例如RVA22版本不强制实现Svnapot拓展，而到了RVA23，该拓展强制需要实现，否则Core不符合RVA23标准。这种规范的出现则在保留灵活性的基础上，规范了Core“实现”的种类。有利于统一硬件厂商的芯片实现，利好软件生态的发展。

3RVA23介绍

RVA23包含user-mode（RVA23U64）和supervisor-mode (RVA23S64)，每个都包含强制实现的Base，强制实现的Extensions，以及部分可选的Extensions。（下面摘自RVA部分规范）

RVA23U64MandatoryBase
RV64IisthemandatorybaseISAforRVA23U64andislittle-endian.Aspertheunprivilegedarchitecturespecification,theecallinstructioncausesarequestedtraptotheexecutionenvironment.

RVA23U64MandatoryExtensions
ThefollowingmandatoryextensionswerepresentinRVA22U64.

MIntegermultiplicationanddivision.

AAtomicinstructions.

FSingle-precisionfloating-pointinstructions.

DDouble-precisionfloating-pointinstructions.

CCompressedInstructions.

ZicsrCSRinstructions.TheseareimpliedbypresenceofF.

ZicntrBasecountersandtimers.

ZihpmHardwareperformancecounters.

ZiccifMainmemoryregionswithboththecacheabilityandcoherencePMAsmustsupportinstructionfetch,andanyinstructionfetchesofnaturallyalignedpower-of-2sizesuptomin(ILEN,XLEN)(i.e.,32bitsforRVA23)areatomic.

ZiccrseMainmemoryregionswithboththecacheabilityandcoherencePMAsmustsupportRsrvEventual.

ZiccamoaMainmemoryregionswithboththecacheabilityandcoherencePMAsmustsupportAMOArithmetic.

ZicclsmMisalignedloadsandstorestomainmemoryregionswithboththecacheabilityandcoherencePMAsmustbesupported.

Za64rsReservationsetsarecontiguous,naturallyaligned,andamaximumof64bytes.

ZihintpausePauseinstruction.

ZbaAddresscomputation.

ZbbBasicbitmanipulation.

ZbsSingle-bitinstructions.

Zic64bCacheblocksmustbe64bytesinsize,naturallyalignedintheaddressspace.

ZicbomCache-BlockManagementOperations.

ZicbopCache-BlockPrefetchOperations.

ZicbozCache-BlockZeroOperations.

ZfhminHalf-PrecisionFloating-pointtransferandconvert.

ZktData-independentexecutiontime.

ThefollowingmandatoryextensionsarenewinRVA23U64:

VVectorExtension.

Note
VwasoptionalinRVA22U64.
ZvfhminVectorFP16conversioninstructions.

ZvbbVectorbit-manipulationinstructions.

ZvktVectordata-independentexecutiontime.

ZihintntlNon-temporallocalityhints.

ZicondConditionalZeroinginstructions.

ZimopMaybeOperations.

ZcmopCompressedMaybeOperations.

ZcbAdditional16bcompressedinstructions.

ZfaAdditionalscalarFPinstructions.

ZawrsWaitonreservationset.

RVA23U64OptionalExtensions
RVA23U64hastenprofileoptions(Zvkng,Zvksg,Zacas,Zvbc,Zfh,Zbc,Zvfh,Zfbfmin,Zvfbfmin,Zvfbfwma).

LocalizedOptions
ThefollowinglocalizedoptionsarenewinRVA23U64:

ZvkngVectorCryptoNISTAlgorithmsincludingGHASH.

ZvksgVectorCryptoShangMiAlgorithmsincludingGHASH.

Note
ThescalarcryptoextensionsZknandZksthatwereoptionsinRVA22arenotoptionsinRVA23.Thegoalisforbothhardwareandsoftwarevendorstomovetousevectorcrypto,asvectorsarenowmandatoryandvectorcryptoissubstantiallyfasterthanscalarcrypto.
Note
WehaveincludedonlytheZvkng/ZvksgoptionswithGHASHtostandardizeonahigherperformancecryptoalternative.Zvbcislistedasadevelopmentoptionforuseinotheralgorithms,andwillbecomemandatory.ScalarZbcisnowlistedasanexpansionoption,i.e.,itwillprobablynotbecomemandatory.
DevelopmentOptions
ThefollowingarenewdevelopmentoptionsintendedtobecomemandatoryinRVA24U64:

ZacasCompare-and-swap

ZvbcVectorcarrylessmultiply.

ExpansionOptions
ThefollowingexpansionoptionswerealsopresentinRVA22U64:

ZfhScalarHalf-PrecisionFloating-Point(FP16).

ThefollowingarenewexpansionoptionsinRVA23U64:

ZbcScalarcarrylessmultiply.

ZvfhVectorhalf-precisionfloating-point(FP16).

ZfbfminScalarBF16FPconversions.

ZvfbfminVectorBF16FPconversions.

ZvfbfwmaVectorBF16wideningmul-add.

TransitoryOptions
TherearenotransitoryoptionsinRVA23U64.

Note
ScalarcryptoisnolongeranoptioninRVA23U64,thoughtheZbcextensionhasnowbeenexposedasanexpansionoption.
RVA23U64Recommendations
Implementationsarestronglyrecommendedtoraiseillegal-instructionexceptionsonattemptstoexecuteunimplementedopcodes.

RVA23S64Profile
TheRVA23S64profilespecifiestheISAfeaturesavailabletoasupervisor-modeexecutionenvironmentin64-bitapplicationsprocessors.RVA23S64isbasedonprivilegedarchitectureversion1.13.

Note
Priv1.13isstillbeingdefined.
RVA23S64MandatoryBase
RV64IisthemandatorybaseISAforRVA23S64andislittle-endian.Theecallinstructionoperatesaspertheunprivilegedarchitecturespecification.Anecallinusermodecausesacontainedtraptosupervisormode.Anecallinsupervisormodecausesarequestedtraptotheexecutionenvironment.

RVA23S64MandatoryExtensions
Thefollowingunprivilegedextensionsaremandatory:

TheRVA23S64mandatoryunprivilegedextensionsincludeallthemandatoryunprivilegedextensionsinRVA23U64.

ZifenceiInstruction-FetchFence.

Note
Zifenceiismandatedasitistheonlystandardwaytosupportinstruction-cachecoherenceinRVA23applicationprocessors.Anewinstruction-cachecoherencemechanismisunderdevelopment(tentativelynamedZjid)whichmightbeaddedasanoptioninthefuture.
Thefollowingprivilegedextensionsaremandatory:

Ss1p13PrivilegedArchitectureversion1.13.

Note
Ss1p13supersedesSs1p12butisnotyetratified.
ThefollowingprivilegedextensionswerealsomandatoryinRVA22S64:

SvbareThesatpmodeBaremustbesupported.

Sv39Page-Based39-bitVirtual-MemorySystem.

SvadePage-faultexceptionsareraisedwhenapageisaccessedwhenAbitisclear,orwrittenwhenDbitisclear.

SsccptrMainmemoryregionswithboththecacheabilityandcoherencePMAsmustsupporthardwarepage-tablereads.

Sstvecdstvec.MODEmustbecapableofholdingthevalue0(Direct).Whenstvec.MODE=Direct,stvec.BASEmustbecapableofholdinganyvalidfour-byte-alignedaddress.

Sstvalastvalmustbewrittenwiththefaultingvirtualaddressforload,store,andinstructionpage-fault,access-fault,andmisalignedexceptions,andforbreakpointexceptionsotherthanthosecausedbyexecutionoftheEBREAKorC.EBREAKinstructions.Forillegal-instructionexceptions,stvalmustbewrittenwiththefaultinginstruction.

SscounterenwForanyhpmcounterthatisnotread-onlyzero,thecorrespondingbitinscounterenmustbewritable.

SvpbmtPage-BasedMemoryTypes

SvinvalFine-GrainedAddress-TranslationCacheInvalidation

Thefollowingarenewmandatoryextensions:

SvnapotNAPOTTranslationContiguity

Note
SvnapotwasoptionalinRVA22.
Sstcsupervisor-modetimerinterrupts.

Note
SstcwasoptionalinRVA22.
SscofpmfCountOverflowandMode-BasedFiltering.

SsnpmPointermasking,withsenvcfg.PMEandhenvcfg.PMEsupporting,atminimum,settingsPMLEN=0andPMLEN=7.

Ssu64xlsstatus.UXLmustbecapableofholdingthevalue2(i.e.,UXLEN=64mustbesupported).

Note
Ssu64xlwasoptionalinRVA22.
HThehypervisorextension.

Note
ThehypervisorwasoptionalinRVA22.
Note
ThefollowingextensionswererequiredwhenthehypervisorwasimplementedinRVA22.
SsstateenSupervisor-modeviewofthestate-enableextension.Thesupervisor-mode(sstateen0-3)andhypervisor-mode(hstateen0-3)state-enableregistersmustbeprovided.

ShcounterenwForanyhpmcounterthatisnotread-onlyzero,thecorrespondingbitinhcounterenmustbewritable.

Shvstvalavstvalmustbewritteninallcasesdescribedaboveforstval.

ShtvalahtvalmustbewrittenwiththefaultingguestphysicaladdressinallcircumstancespermittedbytheISA.

Shvstvecdvstvec.MODEmustbecapableofholdingthevalue0(Direct).Whenvstvec.MODE=Direct,vstvec.BASEmustbecapableofholdinganyvalidfour-byte-alignedaddress.

ShvsatpaAlltranslationmodessupportedinsatpmustbesupportedinvsatp.

ShgatpaForeachsupportedvirtualmemoryschemeSvNNsupportedinsatp,thecorrespondinghgatpSvNNx4modemustbesupported.ThehgatpmodeBaremustalsobesupported.

RVA23S64OptionalExtensions
RVA23S64hastenunprivilegedoptions(Zvkng,Zvksg,Zacas,Zvbc,Zfh,Zbc,Zvfh,Zfbfmin,Zvfbfmin,Zvfbfwma)fromRVA23U64,andsixprivilegedoptions(Sv48,Sv57,Svadu,Zkr,Sdext,Ssstrict).

LocalizedOptions
TherearenoprivilegedlocalizedoptionsinRVA23S64

DevelopmentOptions
TherearenoprivilegeddevelopmentoptionsinRVA23S64.

ExpansionOptions
ThefollowingprivilegedexpansionoptionswerepresentinRVA22S64:

Sv48Page-Based48-bitVirtual-MemorySystem.

Sv57Page-Based57-bitVirtual-MemorySystem.

ZkrEntropyCSR.

ThefollowingarenewprivilegedexpansionoptionsinRVA23S64

SvaduHardwareA/Dbitupdates.

SdextDebugtriggers

SsstrictNonon-conformingextensionsarepresent.AttemptstoexecuteunimplementedopcodesoraccessunimplementedCSRsinthestandardorreservedencodingspacesraisesanillegalinstructionexceptionthatresultsinacontainedtraptothesupervisor-modetraphandler.

Note
SsstrictdoesnotprescribebehaviorforthecustomencodingspacesorCSRs.
TransitoryOptions
TherearenoprivilegedtransitoryoptionsinRVA23S64.

RVA23S64Recommendations
Implementationsarestronglyrecommendedtoraiseillegal-instructionexceptionswhenattemptingtoexecuteunimplementedopcodesoraccessunimplementedCSRs.

4结语

目前RISC-V架构的不完善正在慢慢补全，碎片化的问题正在规整，而RISC-V无法实现高性能的传言也被各个厂商打破，目前不少的软件件大厂也关注RISC-V，也许RISC-V的光明未来正在到来。